This diagram below actually shows how the cache is arranged; each red arrow comes off a slice of cache that's 2.5MB, with the entire structure connected in a ring bus topology that links to the ...

Buffalo Memory’s innovative SATA III SSD is first to implement Spin Torque MRAM as cache memory. Embedded Technology 2013. November 18, 2013 08:03 AM Eastern Standard Time.

New cache organization scheme could dramatically improve ... is the fact that existing memory systems don't ... a block diagram from Intel or AMD will include a single contiguous area and the ...